Conference proceeding
SOC test scheduling using simulated annealing
Proceedings. 21st VLSI Test Symposium, 2003, Vol.2003-, pp.325-330
2003
DOI: 10.1109/VTEST.2003.1197670
Abstract
We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC'02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.
Details
- Title: Subtitle
- SOC test scheduling using simulated annealing
- Creators
- Wei Zou - University of IowaS.M Reddy - University of IowaI PomeranzYu Huang
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings. 21st VLSI Test Symposium, 2003, Vol.2003-, pp.325-330
- Publisher
- IEEE
- DOI
- 10.1109/VTEST.2003.1197670
- ISSN
- 1093-0167
- eISSN
- 2375-1053
- Language
- English
- Date published
- 2003
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197354802771
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