Conference proceeding
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
2008 IEEE Computer Society Annual Symposium on VLSI, pp.257-262
04/2008
DOI: 10.1109/ISVLSI.2008.22
Abstract
Selective hardening aims at achieving maximal soft error rate reduction at reasonable cost by applying hardening techniques to most susceptible circuit nodes only. Logical, electrical and latching-window masking effects must all be considered when calculating the susceptibility of circuit nodes to soft errors. We introduce a scalable selective hardening method based on an approximate calculation of fault detection probabilities at the nodes. Error probability reduction comparable to that obtained by the exact BDD-based algorithm (which is not scalable) can be achieved by setting an over-ambitious optimization target. The run times are negligible even for industrial multiple-million-gates circuits. Existing approaches for calculating electrical and latching-window masking can be readily incorporated into the framework.
Details
- Title: Subtitle
- Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
- Creators
- Ilia Polian - KohlerSudhakar M Reddy - University of FreiburgBernd Becker - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- 2008 IEEE Computer Society Annual Symposium on VLSI, pp.257-262
- DOI
- 10.1109/ISVLSI.2008.22
- ISSN
- 2159-3469
- eISSN
- 2159-3477
- Publisher
- IEEE
- Language
- English
- Date published
- 04/2008
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197173502771
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