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Scaling Sparse Matrix Multiplication on CPU-GPU Nodes
Conference proceeding

Scaling Sparse Matrix Multiplication on CPU-GPU Nodes

Yang Xia, Peng Jiang, Gagan Agrawal and Rajiv Ramnath
2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pp.392-401
05/2021
DOI: 10.1109/IPDPS49936.2021.00047

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Abstract

Multiplication of two sparse matrices (SpGEMM) is a popular kernel behind many numerical solvers, and also features in implementing many common graph algorithms. Though many recent research efforts have focused on implementing SpGEMM efficiently on a single GPU, none of the existing work has considered the case where the memory requirements exceed the size of GPU memory. Similarly, the use of the aggregate computing power of CPU and GPU has also not been addressed for those large matrices. In this paper, we present a framework for scaling SpGEMM computations for matrices that do not fit into GPU memory. We address how the computation and data can be partitioned across kernel executions on GPUs. An important emphasis in our work is overlapping data movement and computation. We achieve this by addressing many challenges, such as avoiding dynamic memory allocations, and re-scheduling data transfers with the computation of chunks. We extend our framework to make efficient use of both GPU and CPU, by developing an efficient work distribution strategy. Our evaluation on 9 large matrices shows that our out-of-core GPU implementation achieves 1.98-3.03X speedups over a state-of-the-art multi-core CPU implementation, our hybrid implementation further achieves speedups up to 3.74x, and that our design choices are directly contributing towards achieving this performance.
 Data transfer Distributed processing Distribution strategy Dynamic scheduling Graphics processing units Memory management Sparse matrices

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