Scan tests with multiple fault activation cycles for delay faults

Zhuo Zhang; Sudhakar M Reddy; Irith Pomeranz; Xijiang Lin; Janusz Rajski

doi:10.1109/VTS.2006.91

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Conference proceeding

Scan tests with multiple fault activation cycles for delay faults

Zhuo Zhang, Sudhakar M Reddy, Irith Pomeranz, Xijiang Lin and Janusz Rajski

24th IEEE VLSI Test Symposium, Vol.2006, pp.6 pp-348

2006

DOI: 10.1109/VTS.2006.91

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Abstract

In this paper we investigate methods to detect delay faults in circuits that use standard scan design. We demonstrate that delay faults at several sites in a circuit cannot be detected using standard launch off capture and launch off shift tests that use two test cycles. However, faults at these sites are detectable using tests that use more than two test cycles. Experimental results on benchmark and industrial circuits that use standard scan design show that substantial numbers of transition delay faults require tests using more than one fault activation cycles to detect them

Benchmark testing

Circuit faults

Circuit testing

Cities and towns

Delay

Design engineering

Electrical fault detection

Fault detection

Graphics

Lab-on-a-chip

Details

Title: Subtitle: Scan tests with multiple fault activation cycles for delay faults
Creators: Zhuo Zhang - University of Iowa
Sudhakar M Reddy - University of Iowa
Irith Pomeranz - Purdue University West Lafayette
Xijiang Lin - Mentor Graphics (United States)
Janusz Rajski - Mentor Graphics (United States)
Resource Type: Conference proceeding
Publication Details: 24th IEEE VLSI Test Symposium, Vol.2006, pp.6 pp-348
DOI: 10.1109/VTS.2006.91
ISSN: 1093-0167
eISSN: 2375-1053
Publisher: IEEE
Language: English
Date published: 2006
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197547502771

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