Seamless - A Latency-Tolerant RISC-Based Multiprocessor Architecture

S.A Fineberg; T.L Casavant; B.H Pease

doi:10.1109/ISCA.1992.753349

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Conference proceeding

Seamless - A Latency-Tolerant RISC-Based Multiprocessor Architecture

S.A Fineberg, T.L Casavant and B.H Pease

[1992] Proceedings the 19th Annual International Symposium on Computer Architecture, pp.432-432

International Symposium and Computer Architecture, 19 (Gold Coast, Queensland, Australia, 05/19/1992–05/21/1992)

1992

DOI: 10.1109/ISCA.1992.753349

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Abstract

The Seamless parallel system being developed at the University of Iowa ECE Department provides a method for providing latency tolerance in physically-distributed memory systems utilizing "off-the-shelf " RISC CPUs without incurring the overhead of multithreading. Seamless encompasses an evolutionary new programming model emphasizing data locality that views communication as data movement rather than message passing I/O. A hardware Locality Manager is added to each processing element to perform this data movement concurrently with computation.

Computer Architecture

Parallel Processing

Cities and towns

Delay

Genetic programming

Hardware

Laboratories

Message passing

Multithreading

Reduced instruction set computing

Details

Title: Subtitle: Seamless - A Latency-Tolerant RISC-Based Multiprocessor Architecture
Creators: S.A Fineberg - University of Iowa
T.L Casavant
B.H Pease
Resource Type: Conference proceeding
Publication Details: [1992] Proceedings the 19th Annual International Symposium on Computer Architecture, pp.432-432
Conference: International Symposium and Computer Architecture, 19 (Gold Coast, Queensland, Australia, 05/19/1992–05/21/1992)
DOI: 10.1109/ISCA.1992.753349
Publisher: IEEE
Language: English
Date published: 1992
Academic Unit: Roy J. Carver Department of Biomedical Engineering; Electrical and Computer Engineering
Record Identifier: 9984198017802771

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