Conference proceeding
Selection of potentially testable path delay faults for test generation
Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), pp.376-384
International Test Conference (ITC) (Atlantic City, New Jersey, USA, 10/03/2000–10/05/2000)
2000
DOI: 10.1109/TEST.2000.894227
Abstract
We present a method of path selection and test generation for path delay faults. The proposed method addresses the fact that logic circuits typically have very large numbers of paths, and a large percentage of these paths are typically untestable. The proposed method selects a set of potentially testable long paths by utilizing non-enumerative identification of untestable paths and removing untestable paths from consideration. Test generation is also applied as part of the proposed method. We demonstrate the effectiveness of the method by presenting results for benchmark circuits.
Details
- Title: Subtitle
- Selection of potentially testable path delay faults for test generation
- Creators
- Atsushi Murakami - Kyushu Institute of TechnologySeiji KajiharaTsutomu SasaoIrith PomeranzSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), pp.376-384
- Conference
- International Test Conference (ITC) (Atlantic City, New Jersey, USA, 10/03/2000–10/05/2000)
- DOI
- 10.1109/TEST.2000.894227
- ISSN
- 1089-3539
- eISSN
- 2378-2250
- Publisher
- IEEE
- Language
- English
- Date published
- 2000
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197917302771
Metrics
8 Record Views