Conference proceeding
Sensitivity levels of test patterns and their usefulness in simulation-based test generation
2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, pp.389-394
2000
DOI: 10.1109/ICCD.2000.878313
Abstract
Pattern sensitivity was proposed earlier as a property to guide simulation-based test generation for combinational or full-scan circuits. Sensitivity is a binary property, i.e., a pattern is either sensitive or not. In this work, we replace the binary sensitivity property by a property that assumes a range of values, called the level of sensitivity. We demonstrate that patterns with high levels of sensitivity tend to detect more faults than patterns with low levels of sensitivity, and therefore, it is important to consider the level of sensitivity of test patterns during test generation. We also describe a procedure for generating sensitive patterns with high levels of sensitivity.
Details
- Title: Subtitle
- Sensitivity levels of test patterns and their usefulness in simulation-based test generation
- Creators
- Irith Pomeranz - University of IowaSudhakar M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- 2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, pp.389-394
- DOI
- 10.1109/ICCD.2000.878313
- Language
- English
- Date published
- 2000
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984231871502771
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