Simulation based test generation for scan designs

I Pomeranz; S.M Reddy

doi:10.1109/ICCAD.2000.896529

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Conference proceeding

Simulation based test generation for scan designs

I Pomeranz and S.M Reddy

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140), Vol.2000-, pp.544-549

2000

DOI: 10.1109/ICCAD.2000.896529

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Abstract

We describe a simulation-based test generation procedure for scan designs. A test sequence generated by this procedure consists of a sequence of one or more primary input vectors embedded between a scan-in operation and a scan-out operation. We consider the set of faults that can be detected by test sequences of this form, compared to the case where scan is applied with every test vector. The proposed procedure constructs test sequences that traverse as many pairs of fault-free/faulty states as possible, and thus avoids the use of branch-and-bound test generation techniques. Additional techniques are incorporated into this basic procedure to enhance its effectiveness.

Circuit faults

Circuit simulation

Circuit testing

Cities and towns

Computational modeling

Design engineering

Fault detection

Flip-flops

Logic circuits

Logic testing

Details

Title: Subtitle: Simulation based test generation for scan designs
Creators: I Pomeranz - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M Reddy
Resource Type: Conference proceeding
Publication Details: IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140), Vol.2000-, pp.544-549
Publisher: IEEE
DOI: 10.1109/ICCAD.2000.896529
ISSN: 1092-3152
Language: English
Date published: 2000
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197071502771

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