Conference proceeding
Speedup analysis for parallel implementation of model of response accuracy and response time in computerized testing
COMPUTATIONAL SCIENCE - ICCS 2007, PT 3, PROCEEDINGS, Vol.4489(3), pp.34-41
Lecture Notes in Computer Science
01/01/2007
DOI: 10.1007/978-3-540-72588-6_5
Abstract
Recently, computerized testing has revolutionized the testing industry by offering an array of benefits for both the examinees and the test users. It potentially enhances the quality of education at all levels. Computerized testing also makes available new types of data such as item-response time and human response at the individual item level. However, the present models of these responses demand much computing time. This paper presents an analysis for a parallel implementation of the models by estimating parallel speedup and efficiency. The model provides an insight into the success of advanced computerized testing study using high performance computing (HPC) technology.
Details
- Title: Subtitle
- Speedup analysis for parallel implementation of model of response accuracy and response time in computerized testing
- Creators
- Tianyou Wang - Univ Iowa, Ctr Adv Study Measurement & Assessment, Coll Educ, Iowa City, IA 52242 USAJun Ni - University of Iowa
- Contributors
- Y Shi (Editor)J Dongarra (Editor)PMA Sloot (Editor)
- Resource Type
- Conference proceeding
- Publication Details
- COMPUTATIONAL SCIENCE - ICCS 2007, PT 3, PROCEEDINGS, Vol.4489(3), pp.34-41
- Publisher
- Springer Nature
- Series
- Lecture Notes in Computer Science
- DOI
- 10.1007/978-3-540-72588-6_5
- ISSN
- 0302-9743
- eISSN
- 1611-3349
- Number of pages
- 2
- Language
- English
- Date published
- 01/01/2007
- Academic Unit
- Center for Advanced Studies in Measurement and Assessment; Mechanical Engineering
- Record Identifier
- 9984627194002771
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