Conference proceeding
Staggered ATPG with capture-per-cycle observation test points
2018 IEEE 36th VLSI Test Symposium (VTS), Vol.2018-, pp.1-6
04/2018
DOI: 10.1109/VTS.2018.8368647
Abstract
This paper presents a new staggered test pattern generation scheme. It produces deterministic stimuli in the course of a test-per-clock-based process by using dedicated capture-per-cycle observation test points. These observation points, once inserted into a design, form dedicated scan chains with the capability of capturing test responses during shift cycles when other regular scan cells are loading test patterns. This new scan infrastructure enables one to generate more compact test patterns, reduce test pattern counts, systematically detect many additional faults, and keep the resultant silicon real-estate at the acceptable level. It appears that original scan cells of a design can provide good observability for staggered test patterns. Thus, capture-per-cycle observation test points are directly inserted at selected scan cells' inputs with a minimal impact on the design. Experimental results obtained for large industrial designs illustrate feasibility of the proposed ATPG and are reported herein.
Details
- Title: Subtitle
- Staggered ATPG with capture-per-cycle observation test points
- Creators
- Yingdi Liu - University of IowaJanusz Rajski - Mentor Graphics (United States)Sudhakar M Reddy - University of IowaJedrzej Solecki - Mentor Graphics (United States)Jerzy Tyszer - Poznań University of Technology
- Resource Type
- Conference proceeding
- Publication Details
- 2018 IEEE 36th VLSI Test Symposium (VTS), Vol.2018-, pp.1-6
- DOI
- 10.1109/VTS.2018.8368647
- eISSN
- 2375-1053
- Publisher
- IEEE
- Language
- English
- Date published
- 04/2018
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197293302771
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