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State persistence: a property for guiding test generation
Conference proceeding

State persistence: a property for guiding test generation

Irith Pomeranz and Sudhakar Reddy
Proceedings of the 19th ACM Great Lakes symposium on vlsi, pp.523-528
GLSVLSI '09
05/10/2009
DOI: 10.1145/1531542.1531660

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Abstract

We study a property of circuit states referred to as persistence. The persistence pi(s) of a state s is the number of next-state variables whose values are specified (0 or 1) when a fully-unspecified primary input vector is applied to the circuit in state s. When a next-state variable Yi is specified under a fully-unspecified primary input vector, there are faults in the input cone of Yi that cannot be detected on Yi. We demonstrate through experimental results that when lower-persistence states are used as scan-in states, the resulting tests detect larger numbers of faults. Low-persistence states are thus preferable as scan-in states during test generation. We also discuss the computation of low-persistence states.
broadside tests scan-based tests test generation transition faults

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