Conference proceeding
Static pin mapping and SOC test scheduling for cores with multiple test sets
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings, Vol.2003-, pp.99-104
2003
DOI: 10.1109/ISQED.2003.1194716
Abstract
An algorithm for mapping core terminals to system-on-a-chip (SOC) I/O pins and scheduling tests in order to achieve cost-efficient concurrent test for core-based designs is presented in this paper. In this work "static" pin mapping and test scheduling for concurrent testing are studied for the case of multiple test sets for each core. The problem is formulated as a constrained two-dimensional bin-packing problem. A heuristic algorithm is then proposed to determine a solution. The objectives driving this solution are geared towards reducing the total test application time of SOC and satisfying the test constraints such as limited number of SOC pins and maximum peak power dissipation specified by core integrators. Experimental results demonstrate the effectiveness of the proposed method.
Details
- Title: Subtitle
- Static pin mapping and SOC test scheduling for cores with multiple test sets
- Creators
- Yu Huang - Mentor GraphicsWu-Tung Cheng - Mentor GraphicsChien-Chung Tsai - Mentor GraphicsN Mukherjee - Mentor GraphicsS.M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Fourth International Symposium on Quality Electronic Design, 2003. Proceedings, Vol.2003-, pp.99-104
- DOI
- 10.1109/ISQED.2003.1194716
- ISSN
- 1948-3287
- eISSN
- 1948-3295
- Publisher
- IEEE
- Language
- English
- Date published
- 2003
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197552702771
Metrics
13 Record Views