Conference proceeding
Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences
16th International Conference on VLSI Design, 2003. Proceedings, Vol.2003-, pp.335-340
2003
DOI: 10.1109/ICVD.2003.1183159
Abstract
We propose a new static compaction procedure for scan circuits that generates a test set with a reduced test application time. The proposed procedure combines the advantages of two earlier static compaction procedures, one that tends to generate large numbers of tests with short primary input sequences, and one that tends to generate small numbers of tests with long primary input sequences. The proposed procedure starts from a test set with a large number of tests and long primary input sequences, and it selects a subset of the tests and subsequences of their primary input sequences. It thus has the flexibility of finding an appropriate balance between the number of tests and the lengths of the primary input sequences in order to minimize the test application time.
Details
- Title: Subtitle
- Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences
- Creators
- I Pomeranz - Purdue University West LafayetteS.M Reddy
- Resource Type
- Conference proceeding
- Publication Details
- 16th International Conference on VLSI Design, 2003. Proceedings, Vol.2003-, pp.335-340
- DOI
- 10.1109/ICVD.2003.1183159
- ISSN
- 1063-9667
- eISSN
- 2380-6923
- Publisher
- IEEE
- Language
- English
- Date published
- 2003
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197275702771
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