Synthesis for Broadside Testability of Transition Faults

I Pomeranz; S.M Reddy

doi:10.1109/VTS.2008.10

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Conference proceeding

Synthesis for Broadside Testability of Transition Faults

I Pomeranz and S.M Reddy

26th IEEE VLSI Test Symposium (vts 2008), pp.221-226

04/2008

DOI: 10.1109/VTS.2008.10

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Abstract

We describe a synthesis-for-testability approach targeting broadside testing of transition faults. We refer to this process as synthesis for broadside testability. Unlike design-for-testability (DFT) procedures that require additional control inputs to implement DFT modes of operation, synthesis for broadside testability uses only the standard scan design and relies on broadside tests to detect target faults. The proposed procedure improves the testability of a circuit by changing next-states of state- transitions from its unreachable states, i.e., states that the circuit cannot enter during functional operation. In this way, it replaces broadside tests of the original circuit with new broadside tests that are more effective in detecting target faults.

broadside tests

Circuit faults

Circuit synthesis

Circuit testing

Combinational circuits

Delay

Design for testability

Electrical fault detection

Fault detection

full-scan circuits

Logic testing

standard scan

Switches

test synthesis

transition faults

Details

Title: Subtitle: Synthesis for Broadside Testability of Transition Faults
Creators: I Pomeranz - Purdue University West Lafayette
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 26th IEEE VLSI Test Symposium (vts 2008), pp.221-226
DOI: 10.1109/VTS.2008.10
ISSN: 1093-0167
eISSN: 2375-1053
Publisher: IEEE
Language: English
Date published: 04/2008
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197182302771

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