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Synthesis of multi-level combinational circuits for complete robust path delay fault testability
Conference proceeding

Synthesis of multi-level combinational circuits for complete robust path delay fault testability

Niraj K Jha, Irith Pomeranz, Sudhakar M Reddy and Robert J Miller
[1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing, pp.280-287
1992
DOI: 10.1109/FTCS.1992.243573

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Abstract

Several synthesis rules for obtaining a multilevel multioutput logic circuit with 100% hazard-free robust testability of path delay faults are explored. In the simplest of these rules, an irredundant two-level implementation of the logic function, which is not robustly testable, is modified to a three-level or a four-level completely robust testable implementation. Algebraic factorization is applied to the modified implementation to obtain a completely robust testable multi level circuit at a relatively low area overhead. This rule was found to make most of the considered Berkeley programmable logic array (PLA) benchmark realizations completely testable. For a small number of cases where this synthesis rule is only partially applicable, another rule is presented, which can guarantee complete testability, but at a slightly higher area overhead. Both these synthesis rules also ensure testability of all multiple stuck-at faults with an easily derivable test set. Four other heuristic synthesis rules that can aid in obtaining a completely robust testable circuit at a lower area overhead in some cases are also presented.< >
 Circuit faults Circuit synthesis Circuit testing Combinational circuits Delay Logic circuits Logic functions Logic testing Programmable logic arrays Robustness

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