TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis

Alejandro Czutro; Ilia Polian; Matthew Lewis; Piet Engelke; Sudhakar M Reddy; Bernd Becker

doi:10.1109/VLSI.Design.2009.20

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Conference proceeding

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis

Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M Reddy and Bernd Becker

2009 22nd International Conference on VLSI Design, pp.227-232

01/2009

DOI: 10.1109/VLSI.Design.2009.20

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Abstract

We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.

Computer Science

Engines

ATPG

Automatic test pattern generation

Circuit faults

Circuit testing

Cities and towns

non-standard fault models

Pattern analysis

SAT

Test pattern generators

Very large scale integration

Details

Title: Subtitle: TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
Creators: Alejandro Czutro - University of Freiburg
Ilia Polian - University of Freiburg
Matthew Lewis - University of Freiburg
Piet Engelke - University of Freiburg
Sudhakar M Reddy - University of Iowa
Bernd Becker - University of Freiburg
Resource Type: Conference proceeding
Publication Details: 2009 22nd International Conference on VLSI Design, pp.227-232
DOI: 10.1109/VLSI.Design.2009.20
ISSN: 1063-9667
eISSN: 2380-6923
Publisher: IEEE
Language: English
Date published: 01/2009
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197069402771

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