Conference proceeding
Techniques for improving the efficiency of sequential circuit test generation
Proceedings of the 1999 IEEE/ACM international conference on computer-aided design, pp.147-151
ICCAD '99
International Conference on Computer Aided Design (ICCAD) (San Jose, California, 11/07/1999 - 11/11/1999)
11/07/1999
DOI: 10.1109/ICCAD.1999.810639
Abstract
New techniques are presented in this paper to improve the efficiency of a test generation procedure for synchronous sequential circuits. These techniques aid the test generation procedure by reducing the search space, carrying out non-chronological backtracking, and reusing the test generation effort. They have been integrated into an existing sequential test generation system MIX to constitute a new system, named MIX-PLUS. The experimental results for the ISCAS-89 and ADDENDUM-93 benchmark circuits demonstrate the effectiveness of these techniques in improving the fault coverage and test generation efficiency.
Details
- Title: Subtitle
- Techniques for improving the efficiency of sequential circuit test generation
- Creators
- Xijiang LinIrith PomeranzSudhakar Reddy
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the 1999 IEEE/ACM international conference on computer-aided design, pp.147-151
- Conference
- International Conference on Computer Aided Design (ICCAD) (San Jose, California, 11/07/1999 - 11/11/1999)
- Publisher
- IEEE Press
- Series
- ICCAD '99
- DOI
- 10.1109/ICCAD.1999.810639
- ISSN
- 1092-3152
- Language
- English
- Date published
- 11/07/1999
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984198006502771
Metrics
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