Conference proceeding
Test application time reduction for scan circuits using limited scan operations
International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720), pp.211-216
2004
DOI: 10.1109/ISQED.2004.1283675
Abstract
We describe a static compaction procedure for full-scan circuits. The procedure accepts a (compact) test set generated for the combinational logic of the circuit and produces a test set with reduced test application time and tester memory, requirements. The reductions are achieved by combining pairs of tests. When a pair of tests is combined, the scan operation required between the two tests is replaced with a limited scan operation. Under a limited scan operation a scan chain of length L is shifted a number of positions S /spl les/ L. As a special case, S = 0 implies that the scan operation between two tests is eliminated altogether. We introduce several techniques to ensure that consideration of test pairs can be done efficiently and results in very high levels of test compaction for benchmark circuits.
Details
- Title: Subtitle
- Test application time reduction for scan circuits using limited scan operations
- Creators
- Yonsang Cho - Purdue University West LafayetteIrith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720), pp.211-216
- DOI
- 10.1109/ISQED.2004.1283675
- Publisher
- IEEE
- Language
- English
- Date published
- 2004
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197262202771
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