Test data volume reduction by test data realignment

Irith Pomeranz; Sudhakar M Reddy

doi:10.1109/ATS.2003.1250851

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Conference proceeding

Test data volume reduction by test data realignment

Irith Pomeranz and Sudhakar M Reddy

2003 Test Symposium, Vol.2003-, pp.434-439

2003

DOI: 10.1109/ATS.2003.1250851

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Abstract

We explore an approach to input test data compression called realignment. Realignment changes a test sequence T consisting of n-bit vectors into a sequence T(m) consisting of m-bit vectors for m /spl ges/ n. It then compresses T(m) instead of T to achieve larger levels of compression for T(m) than for T. By controlling m, realignment provides a range of possible solutions that differ in the data volume reduction and the amount of memory required between the decompressor and the circuit. The memory is required in order to translate m-bit vectors produced by the decompressor into n-bit vectors required by the circuit. We present experimental results to demonstrate this tradeoff for synchronous sequential circuits.

Data compression

Integrated circuit testing

Logic circuit testing

Self-testing

Sequential logic circuits

Very-large-scale integration

Details

Title: Subtitle: Test data volume reduction by test data realignment
Creators: Irith Pomeranz - Purdue University West Lafayette
Sudhakar M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 2003 Test Symposium, Vol.2003-, pp.434-439
Publisher: IEEE
DOI: 10.1109/ATS.2003.1250851
ISSN: 1081-7735
eISSN: 2377-5386
Language: English
Date published: 2003
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197214202771

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