Test generation for synchronous sequential circuits to reduce storage requirements

I Pomeranz; S.M Reddy

doi:10.1109/ATS.1998.741655

Back

Conference proceeding

Test generation for synchronous sequential circuits to reduce storage requirements

I Pomeranz and S.M Reddy

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259), pp.446-451

Asian Test Symposium (Singapore, 12/02/1998 - 12/04/1998)

1998

DOI: 10.1109/ATS.1998.741655

View Online

Abstract

The use of appropriate storage schemes for test patterns and test responses on a tester may result in reduced memory requirements, and thus reduced tester cost. Such storage schemes result in new test compaction objectives beyond the need to reduce the number of test patterns as much as possible. We propose test generation procedures that take such test compaction objectives into account. Experimental results are presented to demonstrate the effectiveness of the proposed procedures in reducing the storage requirements of the resulting test sequences.

Circuit faults

Circuit testing

Cities and towns

Compaction

Costs

Performance evaluation

Sequential analysis

Sequential circuits

Synchronous generators

Test pattern generators

Details

Title: Subtitle: Test generation for synchronous sequential circuits to reduce storage requirements
Creators: I Pomeranz - University of Iowa
S.M Reddy
Resource Type: Conference proceeding
Publication Details: Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259), pp.446-451
Conference: Asian Test Symposium (Singapore, 12/02/1998 - 12/04/1998)
Publisher: IEEE
DOI: 10.1109/ATS.1998.741655
ISSN: 1081-7735
eISSN: 2377-5386
Language: English
Date published: 1998
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197913402771

Metrics

5 Record Views

1 Times Cited - Web of Science