Test of Embedded Content Addressable Memories

P Manikandan; Bjorn B Larsen; Einar J Aas; Sudhakar M Reddy

doi:10.1109/ISED.2010.30

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Conference proceeding

Test of Embedded Content Addressable Memories

P Manikandan, Bjorn B Larsen, Einar J Aas and Sudhakar M Reddy

2010 International Symposium on Electronic System Design, pp.113-118

12/2010

DOI: 10.1109/ISED.2010.30

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Abstract

Delay faults in content addressable memories (CAMs) is a major concern in many applications such as network routers, IP filters, longest prefix matching (LPM) search engines and cache tags where high speed data search is significant. It creates the need for analysis of critical paths and detecting associated faults using minimum number of test patterns. This paper proposes a test method to detect different faults of CAM systems using a newly proposed enhanced power-performance (EPP) cell structure. The proposed CAM faults test (CFT) algorithm is using minimum number of operations such as 5m+2n+4. It covers pseudo CMOS logic faults and cell coupling faults of both search and storage circuitries of CAM cells with improved fault coverage.

Arrays

CAM

Circuit faults

Computer aided manufacturing

critical path

faults

Logic gates

match

mismatch

pseudo CMOS logic

Random access memory

testing

Transistors

write

Details

Title: Subtitle: Test of Embedded Content Addressable Memories
Creators: P Manikandan - Norwegian University of Science and Technology
Bjorn B Larsen - Norwegian University of Science and Technology
Einar J Aas - Norwegian University of Science and Technology
Sudhakar M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 2010 International Symposium on Electronic System Design, pp.113-118
DOI: 10.1109/ISED.2010.30
Publisher: IEEE
Language: English
Date published: 12/2010
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197551802771

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