The cut delay fault model for guiding the generation of n-detection test sets for transition faults

I Pomeranz; S.M Reddy

doi:10.1109/VLSID.2006.160

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Conference proceeding

The cut delay fault model for guiding the generation of n-detection test sets for transition faults

I Pomeranz and S.M Reddy

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), Vol.2006, pp.4 pp-831

2006

DOI: 10.1109/VLSID.2006.160

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Abstract

We define a new transition fault model to guide the generation of n-detection test sets for transition faults. The model is referred to as the cut delay fault model. Under a cut delay fault, a transition fault on a line c/sub 0/ is detected while certain other lines in the circuit assume specific values. The lines involved in a cut delay fault form a cut or a subset of a cut. Each transition fault is associated with several combinations of values on the cut, and it is thus detected by several different tests.

Circuit faults

Circuit testing

Cities and towns

Delay

Electrical fault detection

Fault detection

Details

Title: Subtitle: The cut delay fault model for guiding the generation of n-detection test sets for transition faults
Creators: I Pomeranz - Purdue University West Lafayette
S.M Reddy - University of Iowa
Resource Type: Conference proceeding
Publication Details: 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), Vol.2006, pp.4 pp-831
DOI: 10.1109/VLSID.2006.160
ISSN: 1063-9667
eISSN: 2380-6923
Publisher: IEEE
Language: English
Date published: 2006
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197212302771

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