Conference proceeding
Transistor level test generation for MOS circuits
Proceedings of the 22nd ACM/IEEE Design Automation Conference, pp.825-828
DAC '85
06/01/1985
DOI: 10.1109/DAC.1985.1586046
Abstract
Due to inaccuracies in gate level models of VLSI digital circuits, current practice is to use transistor level simulators to analyze VLSI digital circuits. The inaccuracies of gate level models are even more severe when faults in digital circuits are considered. For this reason, recently several researchers have proposed the use of test pattern generation from digital circuits described at the transistor level. In this paper an efficient test pattern generation procedure for digital circuits described at the transistor level is given.
Details
- Title: Subtitle
- Transistor level test generation for MOS circuits
- Creators
- Madhukar ReddySudhakar ReddyPrathima Agrawal
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings of the 22nd ACM/IEEE Design Automation Conference, pp.825-828
- Publisher
- IEEE Press
- Series
- DAC '85
- DOI
- 10.1109/DAC.1985.1586046
- ISSN
- 0738-100X
- eISSN
- 2374-8818
- Language
- English
- Date published
- 06/01/1985
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197106802771
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