Transistor stuck-on fault detection tests for digital CMOS circuits

Xijiang Lin; Sudhakar M Reddy; Janusz Rajski

doi:10.1109/ETS.2016.7519329

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Conference proceeding

Transistor stuck-on fault detection tests for digital CMOS circuits

Xijiang Lin, Sudhakar M Reddy and Janusz Rajski

2016 21th IEEE European Test Symposium (ETS), Vol.2016-, pp.1-6

05/2016

DOI: 10.1109/ETS.2016.7519329

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Abstract

Typically IDDQ measurement based tests are used to detect transistor-stuck-on (TSON) faults in digital CMOS circuits. As the minimum feature sizes of digital VLSI circuits are reduced and the magnitudes of static current of VLSI chips increase, detection of TSON faults using IDDQ measurements is becoming difficult if not impossible. For this reason voltage based tests, called logic tests in this work, are being investigated. In this work we propose generation of logic tests based on Boolean functions implemented by the gates in CMOS digital logic circuits. We also show that, when available, the tests proposed in this work should be preferred over earlier proposed IDDQ based tests. Experimental results on ISCAS-89 and ITC'99 benchmark circuits demonstrate the effectiveness of the proposed logic tests.

Circuit faults

CMOS integrated circuits

Fault Detection

Logic gates

Logic testing

Maximal False and Minimal True Vertices

Resistance

Test Generation

Transistor Stuck-on Faults

Transistors

Unate Functions

Voltage measurement

Details

Title: Subtitle: Transistor stuck-on fault detection tests for digital CMOS circuits
Creators: Xijiang Lin - Mentor Graphics
Sudhakar M Reddy - University of Iowa
Janusz Rajski - Mentor Graphics
Resource Type: Conference proceeding
Publication Details: 2016 21th IEEE European Test Symposium (ETS), Vol.2016-, pp.1-6
DOI: 10.1109/ETS.2016.7519329
ISSN: 1530-1877
eISSN: 1558-1780
Publisher: IEEE
Language: English
Date published: 05/2016
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197556602771

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