Conference proceeding
VERSE: a vector replacement procedure for improving test compaction in synchronous sequential circuits
Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), pp.250-255
1999
DOI: 10.1109/ICVD.1999.745156
Abstract
Static test compaction procedures for synchronous sequential circuits may saturate and be unable to further reduce the test sequence length before the test length reaches its minimum value, resulting in test sequences that may be longer than necessary. We propose a method to take a static compaction procedure out of saturation and allow it to continue reducing the test sequence length. The proposed method is based on the replacement of test vectors in the test sequence every time the compaction procedure reaches saturation. Test vector replacement is done such that the fault coverage of the sequence is maintained. After one or more test vectors are replaced, the test sequence is different from the one obtained after the compaction procedure saturated, and the compaction procedure can be applied to further reduce the test length. Experimental results with an effective static compaction procedure demonstrate that reductions in test length can be obtained by the proposed vector replacement method.
Details
- Title: Subtitle
- VERSE: a vector replacement procedure for improving test compaction in synchronous sequential circuits
- Creators
- Irith Pomeranz - Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USASudhakar M Reddy - University of Iowa
- Resource Type
- Conference proceeding
- Publication Details
- Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), pp.250-255
- Publisher
- IEEE
- DOI
- 10.1109/ICVD.1999.745156
- ISSN
- 1063-9667
- eISSN
- 2380-6923
- Language
- English
- Date published
- 1999
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197189802771
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