- Title: Subtitle
- An automatic test pattern generator for delay faults in logic circuits
- Creators
- Srinivas Patil - University of Iowa
- Contributors
- Sudhakar M Reddy (Advisor) - University of Iowa, Electrical and Computer Engineering
- Resource Type
- Thesis
- Degree Awarded
- Master of Science (MS), University of Iowa
- Degree in
- Electrical and Computer Engineering
- Date degree season
- Spring 1987
- DOI
- 10.25820/etd.008515
- Publisher
- University of Iowa
- Number of pages
- vii, 105 pages
- Copyright
- No known copyright restrictions
- Comment
This thesis has been optimized for improved web viewing. If you require the original version, contact the University Archives at the University of Iowa: https://www.lib.uiowa.edu/sc/contact/
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9985224427202771
Thesis
An automatic test pattern generator for delay faults in logic circuits
University of Iowa
Master of Science (MS), University of Iowa
Spring 1987
DOI: 10.25820/etd.008515
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