Thesis
Impact of Layout and Technology on VLSI Circuit Testability
University of Iowa
Master of Science (MS), University of Iowa
Summer 1984
Abstract
With the evaluation of VLSI, Testability is becoming a growing concern. MOS (CMOS/NMOS) technology is emerging as the pre-eminent VLSI Processing technology. The physical faults such as bridges, shorts and opens are growingly becoming more and more important and are not modeled well by the classical Stuck-at-faults. Some faults possible on the logical diagram have no physical counterparts and faults in the physical circuit may not be representable in the logic domain. In this project we examine the relationship between these physical faults and the circuit layout configuration and the technology. There is an imperative need to extract information from the circuit layout and technology and use it in interpreting the gate level testability measures.
Details
- Title: Subtitle
- Impact of Layout and Technology on VLSI Circuit Testability
- Creators
- Malladi V R J V V Prasad - University of Iowa
- Contributors
- John P Robinson (Supervisor) - University of Iowa
- Resource Type
- Thesis
- Project Type
- Master’s Project
- Degree Awarded
- Master of Science (MS), University of Iowa
- Degree in
- Electrical and Computer Engineering
- Date degree season
- Summer 1984
- Publisher
- University of Iowa
- Number of pages
- 44 pages
- Copyright
- No known copyright restrictions
- Comment
This thesis has been optimized for improved web viewing. If you require the original version, contact the University Archives at the University of Iowa: https://www.lib.uiowa.edu/sc/contact/
- Language
- English
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9985224326102771
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