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t1993_r688-o
Delayed release, Embargo ends: 01/01/2143
- Title: Subtitle
- The bus interface logic for a latency-tolerant RISC-based multiprocessor architecture
- Creators
- Michelle Lee Roderick - University of Iowa
- Resource Type
- Thesis
- Degree Awarded
- Master of Science (MS), University of Iowa
- Degree in
- Electrical and Computer Engineering
- Publisher
- University of Iowa
- Number of pages
- v, 99 pages
- Comment
This thesis has been optimized for improved web viewing. If you require the original version, contact the University Archives at the University of Iowa: https://www.lib.uiowa.edu/sc/contact/
- Language
- English
- Date copyrighted
- 1993
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9985224324702771