Journal article
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
IEEE transactions on computers, Vol.C-27(5), pp.455-459
05/1978
DOI: 10.1109/TC.1978.1675126
Abstract
To improve the reliability of computer memories error-correcting and/or error-detecting codes have been successfully used. To provide for error control in systems organized to have b bits per card a new class of codes for simultaneous error correction and error detection is given.
Details
- Title: Subtitle
- A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
- Creators
- Sudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.C-27(5), pp.455-459
- Publisher
- IEEE
- DOI
- 10.1109/TC.1978.1675126
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 05/1978
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197457802771
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