Journal article
A Design Procedure for Fault-Locatable Switching Circuits
IEEE transactions on computers, Vol.C-21(12), pp.1421-1426
12/1972
DOI: 10.1109/T-C.1972.223517
Abstract
A technique to design fault-locatable combinational switching circuits is given. The networks resulting from the application of the proposed technique have at most three levels of gates.
Details
- Title: Subtitle
- A Design Procedure for Fault-Locatable Switching Circuits
- Creators
- S.M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.C-21(12), pp.1421-1426
- Publisher
- IEEE
- DOI
- 10.1109/T-C.1972.223517
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 12/1972
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197525802771
Metrics
6 Record Views