Journal article
A Low Power Pseudo-Random BIST Technique
Journal of electronic testing, Vol.19(6), pp.637-644
12/2003
DOI: 10.1023/A:1027470721780
Abstract
Peak power consumption during testing is an important concern. For scan designs, a high level of switching activity is created in the circuit during scan shifts, which increases power consumption considerably. In this paper we propose a pseudo-random BIST scheme for scan designs, which reduces the peak power consumption as well as the average power consumption as measured by the switching activity in the circuit. The method reduces the switching activity in the scan chains and the activity in the circuit under test by limiting the scan shifts to a portion of the scan chain structure using scan chain disable. Experimental results on various benchmark circuits demonstrate that the technique reduces the switching activity caused by scan shifts.
Details
- Title: Subtitle
- A Low Power Pseudo-Random BIST Technique
- Creators
- Nadir Basturkmen - University of IowaSudhakar Reddy - University of IowaIrith Pomeranz - Purdue University West Lafayette
- Resource Type
- Journal article
- Publication Details
- Journal of electronic testing, Vol.19(6), pp.637-644
- DOI
- 10.1023/A:1027470721780
- ISSN
- 0923-8174
- eISSN
- 1573-0727
- Publisher
- Kluwer Academic Publishers
- Language
- English
- Date published
- 12/2003
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984196963102771
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