Journal article
A Testable Design of Iterative Logic Arrays
IEEE transactions on computers, Vol.C-30(11), pp.833-841
11/1981
DOI: 10.1109/TC.1981.1675714
Abstract
Testable design of unilateral iterative logic arrays (ILA) of combinational cells under the assumption of a single cell failure is considered. The concepts of one-step testability and one-step C-testability are introduced. Methods to modify the basic cell flow table so as to facilitate fault detection and location are given. It is shown that if no directly observable outputs from each cell are available, then it is possible to augment the cell flow table by the addition of a fixed number (≤4) of columns and a row so that a faulty cell can be located by a test of length proportional to log2p, where p is the number of cells in the array. However, if directly observable outputs are available from each cell, then the test length is shown to be independent of the array length to locate a faulty cell.
Details
- Title: Subtitle
- A Testable Design of Iterative Logic Arrays
- Creators
- R Parthasarathy - University of IowaSudhakar M Reddy
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.C-30(11), pp.833-841
- Publisher
- IEEE
- DOI
- 10.1109/TC.1981.1675714
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 11/1981
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197106702771
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