Journal article
A built-in self-test method for diagnosis of synchronous sequential circuits
IEEE transactions on very large scale integration (VLSI) systems, Vol.9(2), pp.290-296
2001
DOI: 10.1109/92.924046
Abstract
We propose an approach for built-in fault diagnosis of synchronous sequential circuits. The proposed approach distinguishes faults based on their detection by modified versions of a fault detection test sequence generated on-chip. The modified versions are defined by one-bit-wide auxiliary sequences, also generated on-chip. The auxiliary sequences indicate which test vectors of the fault detection test sequence need to be applied to the circuit. Experimental results presented indicate that the proposed on-chip test generation method is effective in achieving high levels of diagnostic resolution.
Details
- Title: Subtitle
- A built-in self-test method for diagnosis of synchronous sequential circuits
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on very large scale integration (VLSI) systems, Vol.9(2), pp.290-296
- DOI
- 10.1109/92.924046
- ISSN
- 1063-8210
- eISSN
- 1557-9999
- Publisher
- Institute of Electrical and Electronics Engineers
- Language
- English
- Date published
- 2001
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197342302771
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