A data compression technique for built-in self-test

S.M Reddy; K.K Saluja; M.G Karpovsky

doi:10.1109/12.2271

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A data compression technique for built-in self-test

Journal article

Peer reviewed

A data compression technique for built-in self-test

S.M Reddy, K.K Saluja and M.G Karpovsky

IEEE transactions on computers, Vol.37(9), pp.1151-1156

09/1988

DOI: 10.1109/12.2271

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Abstract

A data compression technique called self-testable and error-propagating space compression is proposed and analyzed. Faults in a realization of Exclusive-OR and Exclusive-NOR gates are analyzed, and the use of these gates in the design of self-testing and error propagating space compressors is discussed. It is argued that the proposed data-compression technique reduce the hardware complexity in built-in self-test (BIST) logic designs using external tester environments.< >

Automatic testing

Built-in self-test

Circuit faults

Circuit testing

Compressors

Computer errors

Data compression

Logic testing

Sorting

System testing

Details

Title: Subtitle: A data compression technique for built-in self-test
Creators: S.M Reddy - University of Iowa
K.K Saluja - University of Wisconsin–Madison
M.G Karpovsky - Boston University
Resource Type: Journal article
Publication Details: IEEE transactions on computers, Vol.37(9), pp.1151-1156
Publisher: IEEE
DOI: 10.1109/12.2271
ISSN: 0018-9340
eISSN: 1557-9956
Language: English
Date published: 09/1988
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197345202771

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