Journal article
A new approach to the design of testable PLA's
IEEE transactions on computers, Vol.36(2), pp.201-211
1987
DOI: 10.1109/TC.1987.1676882
Abstract
Programmable logic arrays (PLA's) are extensively used to realize area efficient combinational logic circuits. As the size of the PLA's increases, a cost-effective way to test them is to realize testable PLA's. In this paper a new approach to the design of testable PLA's is presented. The proposed method leads to testable PLA's with minimal area penalty and small number of tests that can be obtained as a byproduct of the synthesis procedure, or can be directly obtained from the personality of the PLA's, thus simplifying the test derivation step. Results of an experiment involving 56 PLA's, to compare the test set sizes of different testable PLA designs (including the design proposed here) as well as the size of tests derived to detect single faults by algorithmic procedures are also reported. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
Details
- Title: Subtitle
- A new approach to the design of testable PLA's
- Creators
- S. M Reddy - Univ. Iowa, dep. electrical computer eng., Iowa City IA 52242, United StatesDONG SAM HA - Univ. Iowa, dep. electrical computer eng., Iowa City IA 52242, United States
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.36(2), pp.201-211
- Publisher
- Institute of Electrical and Electronics Engineers
- DOI
- 10.1109/TC.1987.1676882
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 1987
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197206102771
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