Journal article
A storage-based built-in test pattern generation method for scan circuits based on partitioning and reduction of a precomputed test set
IEEE transactions on computers, Vol.51(11), pp.1282-1293
11/01/2002
DOI: 10.1109/TC.2002.1047753
Abstract
We describe a built-in test pattern generation method for scan circuits. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The sets are stored on-chip and the on-chip test set is obtained by implementing the Cartesian product of the various sets. The sets are reduced as much as possible before they are stored on-chip in order to reduce the storage requirements and the test application time. We describe two schemes for reducing the set sizes, one where each set stores the values of one subset of primary inputs or state variables and one where a single set is used to store values of different subsets of state variables. We demonstrate the effectiveness of the proposed method as a stand-alone procedure and as part of a scheme where random patterns are first applied to detect easy-to-detect faults. In the latter case, the proposed method is applied to detect the hard-to-detect faults that remain undetected.
Details
- Title: Subtitle
- A storage-based built-in test pattern generation method for scan circuits based on partitioning and reduction of a precomputed test set
- Creators
- Irith PomeranzSudhakar M Reddy
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.51(11), pp.1282-1293
- Publisher
- Institute of Electrical and Electronics Engineers, Inc
- DOI
- 10.1109/TC.2002.1047753
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 11/01/2002
- Description audience
- Trade; Academic
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197915002771
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