Aliasing computation using fault simulation with fault dropping

I Pomeranz; S.M Reddy

doi:10.1109/12.368001

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Aliasing computation using fault simulation with fault dropping

Journal article

Peer reviewed

Aliasing computation using fault simulation with fault dropping

I Pomeranz and S.M Reddy

IEEE transactions on computers, Vol.44(1), pp.139-144

01/1995

DOI: 10.1109/12.368001

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Abstract

It is generally thought that accurate analysis of aliasing requires non-fault dropping fault simulation. We show that fault dropping is possible when computing the exact aliasing of modeled faults for common output response compression circuits. The fault dropping process is most effective when the test set size is small. Extensions to large test sets are also considered. We present a fault simulation procedure that takes maximum advantage of fault dropping and present experimental results to support its effectiveness.< >

Analytical models

Built-in self-test

Circuit faults

Circuit simulation

Circuit testing

Cities and towns

Computational modeling

Feedback circuits

Hardware

Linear feedback shift registers

Details

Title: Subtitle: Aliasing computation using fault simulation with fault dropping
Creators: I Pomeranz - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Journal article
Publication Details: IEEE transactions on computers, Vol.44(1), pp.139-144
Publisher: IEEE
DOI: 10.1109/12.368001
ISSN: 0018-9340
eISSN: 1557-9956
Language: English
Date published: 01/1995
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197314202771

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