Journal article
Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of input sequences using single and multiple fault detection times
IEEE transactions on computers, Vol.51(4), pp.409-419
04/2002
DOI: 10.1109/12.995451
Abstract
We describe an on-chip test generation scheme for synchronous sequential circuits that allows at-speed testing of such circuits. The proposed scheme is based on loading of (short) input sequences into an on-chip memory and expansion of these sequences on-chip into test sequences. Complete coverage of modeled faults is achieved by basing the selection of the loaded sequences on a deterministic test sequence T/sub 0/ and ensuring that every fault detected by T/sub 0/ is detected by the expanded version of at least one loaded sequence. Specifically, each input sequence S is constructed based on a different fault f and is extracted from T/sub 0/ around a time unit where f is detected by T/sub 0/. Experimental results presented for benchmark circuits show that the length of the sequence that needs to be stored on-chip at any given time is, on the average, 11 percent of the length of T/sub 0/ and that the total length of all the loaded sequences is, on the average, 48 percent of the length of T/sub 0/. These results are obtained by extracting each sequence S around the first detection time of a target fault f. These results are further improved by considering several time units for every target fault f and selecting the shortest possible sequence based on f.
Details
- Title: Subtitle
- Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of input sequences using single and multiple fault detection times
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.51(4), pp.409-419
- DOI
- 10.1109/12.995451
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Publisher
- IEEE
- Language
- English
- Date published
- 04/2002
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197525602771
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