Journal article
COMPACTEST: a method to generate compact test sets for combinational circuits
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.12(7), pp.1040-1049
07/1993
DOI: 10.1109/43.238040
Abstract
Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics.< >
Details
- Title: Subtitle
- COMPACTEST: a method to generate compact test sets for combinational circuits
- Creators
- I Pomeranz - University of IowaL.N Reddy - University of IowaS.M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.12(7), pp.1040-1049
- Publisher
- IEEE
- DOI
- 10.1109/43.238040
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Language
- English
- Date published
- 07/1993
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197274002771
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