Journal article
Complete Test Sets for Logic Functions
IEEE transactions on computers, Vol.C-22(11), pp.1016-1020
11/1973
DOI: 10.1109/T-C.1973.223638
Abstract
The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted networks, called unate gate networks. It is further indicated that even in the presence of redundancies in the network, the test sets given remain valid.
Details
- Title: Subtitle
- Complete Test Sets for Logic Functions
- Creators
- S.M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.C-22(11), pp.1016-1020
- Publisher
- IEEE
- DOI
- 10.1109/T-C.1973.223638
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 11/1973
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197447602771
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