Journal article
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.14(12), pp.1496-1504
1995
DOI: 10.1109/43.476580
Abstract
This paper presents new cost-effective heuristics for the generation of minimal test sets, Both dynamic techniques, which are introduced into the test generation process, and a static technique, which is applied to already generated test sets, are used. The dynamic compaction techniques maximize the number of faults that a new test vector detects out of the yet-undetected Faults as well as out of the already-detected ones. Thus, they reduce the number of tests and allow tests generated earlier in the test generation process to be dropped. The static compaction technique replaces N test vectors by M < M test vectors, without loss of fault coverage, During test generation, we also fmd a lower hound on test set size. Experimental results demonstrate the effectiveness of the proposed techniques.
Details
- Title: Subtitle
- Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
- Creators
- S KAJIHARA - Osaka UniversityI POMERANZK KINOSHITAS M REDDY
- Resource Type
- Journal article
- Publication Details
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.14(12), pp.1496-1504
- DOI
- 10.1109/43.476580
- ISSN
- 0278-0070
- Language
- English
- Date published
- 1995
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984232098002771
Metrics
12 Record Views