Design-for-testability for path delay faults in large combinational circuits using test points

I Pomeranz; S.M Reddy

doi:10.1109/43.703823

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Design-for-testability for path delay faults in large combinational circuits using test points

Journal article

Peer reviewed

Design-for-testability for path delay faults in large combinational circuits using test points

I Pomeranz and S.M Reddy

IEEE transactions on computer-aided design of integrated circuits and systems, Vol.17(4), pp.333-343

04/1998

DOI: 10.1109/43.703823

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Abstract

We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. In addition, by breaking an untestable path into two or more testable subpaths, it is possible to obtain a fully testable circuit. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. When the number of paths is sufficiently small, and if the test generation procedure to be used for the circuit is known, a procedure is given to perform test-point insertion directly targeting the path delay faults that are still untestable. Experimental results are presented to demonstrate the effectiveness of the proposed methods in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

Benchmark testing

Circuit faults

Circuit testing

Clocks

Combinational circuits

Delay

Electrical fault detection

Fault detection

Performance evaluation

Timing

Details

Title: Subtitle: Design-for-testability for path delay faults in large combinational circuits using test points
Creators: I Pomeranz - University of Iowa
S.M Reddy - University of Iowa
Resource Type: Journal article
Publication Details: IEEE transactions on computer-aided design of integrated circuits and systems, Vol.17(4), pp.333-343
Publisher: IEEE
DOI: 10.1109/43.703823
ISSN: 0278-0070
eISSN: 1937-4151
Language: English
Date published: 04/1998
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197309802771

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