Journal article
Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits
Journal of systems architecture, Vol.47(3), pp.357-373
2001
DOI: 10.1016/S1383-7621(00)00054-0
Abstract
We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modifications to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and performance overheads. The proposed technique allows us to achieve complete coverage of detectable delay faults by allowing any two-pattern test to be applied to the circuit through its functional path. In addition to the basic approach, we study the proposed procedure in the presence of a constraint that requires that extra logic would not be placed on the critical paths of the circuit.
Details
- Title: Subtitle
- Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- Journal of systems architecture, Vol.47(3), pp.357-373
- DOI
- 10.1016/S1383-7621(00)00054-0
- ISSN
- 1383-7621
- eISSN
- 1873-6165
- Publisher
- Elsevier B.V
- Language
- English
- Date published
- 2001
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197456002771
Metrics
6 Record Views