Journal article
Design of robustly testable combinational logic circuits
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.10(8), pp.1036-1048
1991
DOI: 10.1109/43.85740
Abstract
An integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests is proposed. Robustly testable static CMOS primitive logic circuit designs are presented for any arbitrary combinational logic function. They require no special gates, and fan-in and fan-out constraints do not affect the designs. Extra controllable inputs or additional hardware to achieve testability was not used. It is demonstrated that the method guarantees the design of CMOS logic circuits in which all path delay faults are locatable.
Details
- Title: Subtitle
- Design of robustly testable combinational logic circuits
- Creators
- SANDIP Kundu - IBMSudhakar M Reddy - University of IowaNiraj K Jha - Electrical Engineering
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.10(8), pp.1036-1048
- Publisher
- Institute of Electrical and Electronics Engineers
- DOI
- 10.1109/43.85740
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Language
- English
- Date published
- 1991
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197260802771
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