Detection of bridging faults in programmable logic arrays

K.K Saluja; C.-Y Liu; S.M Reddy

doi:10.1049/el:19920774

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Detection of bridging faults in programmable logic arrays

Journal article

Open access

Peer reviewed

Detection of bridging faults in programmable logic arrays

K.K Saluja, C.-Y Liu and S.M Reddy

Electronics letters, Vol.28(13), pp.1226-1228

1992

DOI: 10.1049/el:19920774

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Abstract

A test set and a testable design for MOS PLAs are proposed. The new design, which modifies a PLA by adding one extra line in the AND plane and one extra line in the OR plane, can detect bridging faults. Furthermore, the design modification requires very low area overhead and is independent of the personality of the PLA under test. © 1992, The Institution of Electrical Engineers. All rights reserved.

Details

Title: Subtitle: Detection of bridging faults in programmable logic arrays
Creators: K.K Saluja - University of Wisconsin–Madison
C.-Y Liu - University of Wisconsin–Madison
S.M Reddy - University of Iowa
Resource Type: Journal article
Publication Details: Electronics letters, Vol.28(13), pp.1226-1228
DOI: 10.1049/el:19920774
ISSN: 0013-5194
Language: English
Date published: 1992
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197261502771

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