Embedded Deterministic Test Points

Cesar Acero; Derek Feltham; Yingdi Liu; Elham Moghaddam; Nilanjan Mukherjee; Marek Patyra; Janusz Rajski; Sudhakar M Reddy; Jerzy Tyszer; Justyna Zawada

doi:10.1109/TVLSI.2017.2717844

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Journal article

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Embedded Deterministic Test Points

Cesar Acero, Derek Feltham, Yingdi Liu, Elham Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M Reddy, Jerzy Tyszer and Justyna Zawada

IEEE transactions on very large scale integration (VLSI) systems, Vol.25(10), pp.2949-2961

10/2017

DOI: 10.1109/TVLSI.2017.2717844

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Abstract

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of 2×-4× compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

Automatic test pattern generation

Circuit faults

Computational modeling

Design for testability

embedded test

Logic gates

scan-based testing

Signal resolution

Silicon

test application time

test data compression

test points

Details

Title: Subtitle: Embedded Deterministic Test Points
Creators: Cesar Acero - Intel
Derek Feltham - Intel
Yingdi Liu - University of Iowa
Elham Moghaddam - Mentor Graphics
Nilanjan Mukherjee - Mentor Graphics
Marek Patyra - Intel
Janusz Rajski - Mentor Graphics
Sudhakar M Reddy - University of Iowa
Jerzy Tyszer - Poznań University of Technology
Justyna Zawada - Poznań University of Technology
Resource Type: Journal article
Publication Details: IEEE transactions on very large scale integration (VLSI) systems, Vol.25(10), pp.2949-2961
DOI: 10.1109/TVLSI.2017.2717844
ISSN: 1063-8210
eISSN: 1557-9999
Publisher: IEEE
Grant note: DS-811/17 / Polish Ministry of Science and Higher Education
Language: English
Date published: 10/2017
Academic Unit: Electrical and Computer Engineering
Record Identifier: 9984197192202771

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