Journal article
Error-Control Techniques for Logic Processors
IEEE transactions on computers, Vol.C-21(12), pp.1331-1336
12/1972
DOI: 10.1109/T-C.1972.223504
Abstract
A new error-control technique for logic processors is given. The proposed technique uses Reed-Muller codes (RMC's). The design scheme given has better efficiency than the schemes proposed earlier. The improved efficiency is obtained by relaxing a basic assumption originally made by Elias. Furthermore, it is shown that the efficiency of the proposed scheme asymptotically approaches the maximum efficiency achievable by a practical though restricted class of error-control schemes. Reliability of the proposed scheme is studied.
Details
- Title: Subtitle
- Error-Control Techniques for Logic Processors
- Creators
- D.K Pradhan - University of IowaS.M Reddy
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computers, Vol.C-21(12), pp.1331-1336
- Publisher
- IEEE
- DOI
- 10.1109/T-C.1972.223504
- ISSN
- 0018-9340
- eISSN
- 1557-9956
- Language
- English
- Date published
- 12/1972
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197421002771
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