Journal article
Fixed-State Tests for Delay Faults in Scan Designs
IEEE transactions on very large scale integration (VLSI) systems, Vol.19(1), pp.142-146
2011
DOI: 10.1109/TVLSI.2009.2030811
Abstract
One of the methods to reduce the power dissipation during scan shifting is based on holding the state inputs to the combinational logic of a circuit constant for the duration of a scan operation. We note that this method also allows a new type of two-pattern scan-based tests to be applied. We refer to these tests as fixed-state tests. These tests have several properties that make them effective as complements to skewed-load and broadside tests, and also allows them to be computed efficiently. We discuss these properties in the context of transition faults. We describe procedures for selecting the constant vector for the state inputs during a scan operation, and for generating fixed-state tests. We present experimental results to demonstrate the transition fault coverage improvements possible with these tests. © 2006 IEEE.
Details
- Title: Subtitle
- Fixed-State Tests for Delay Faults in Scan Designs
- Creators
- Irith Pomeranz - Purdue University West LafayetteSudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on very large scale integration (VLSI) systems, Vol.19(1), pp.142-146
- DOI
- 10.1109/TVLSI.2009.2030811
- ISSN
- 1063-8210
- eISSN
- 1557-9999
- Publisher
- Institute of Electrical and Electronics Engineers
- Language
- English
- Date published
- 2011
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197459202771
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