Journal article
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.39(6), pp.1340-1345
06/2020
DOI: 10.1109/TCAD.2019.2921345
Abstract
A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs.
Details
- Title: Subtitle
- Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run
- Creators
- Yi-Cheng Kung - National Cheng Kung UniversityKuen-Jong Lee - National Cheng Kung UniversitySudhakar M Reddy - University of Iowa
- Resource Type
- Journal article
- Publication Details
- IEEE transactions on computer-aided design of integrated circuits and systems, Vol.39(6), pp.1340-1345
- Publisher
- IEEE
- DOI
- 10.1109/TCAD.2019.2921345
- ISSN
- 0278-0070
- eISSN
- 1937-4151
- Grant note
- MOST 107-2218-E-006-025 / Ministry of Science and Technology of Taiwan (10.13039/501100004663)
- Language
- English
- Date published
- 06/2020
- Academic Unit
- Electrical and Computer Engineering
- Record Identifier
- 9984197535702771
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