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Improved n-Detection Test Sequences Under Transparent Scan
Journal article   Peer reviewed

Improved n-Detection Test Sequences Under Transparent Scan

Irith Pomeranz and Sudhakar M Reddy
IEEE transactions on computer-aided design of integrated circuits and systems, Vol.25(11), pp.2492-2501
11/2006
DOI: 10.1109/TCAD.2006.881334

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Abstract

Logic Microprocessors Circuit faults Circuit testing Clocks Compaction Design automation Electrical fault detection Fault detection scan design Switches test generation

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